Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /USB /GCTL

Disable clock gating. This bit is set to 0x1 and the controller is in Low-Power mode, internal clock gating is disabled. This bit can be set to 0x1 after power-on reset.

Hibernation enable status at the global level. If hibernation is not enabled through this bit, the PMU immediately accepts the D0 -> D3 and D3 -> D0 power state change requests, but does not save or restore any controller state. In addition, the PMUs never drive the PHY interfaces and let the controller continue to drive the PHY interfaces.

Disable scrambling.

Scale-Down mode. Keep at 0x0.

RAM clock (RAM_CLK) select.

0 (Val_0x0): AHB bus clock (BUS_CLK)

2 (Val_0x2): In Host mode, the controller switches RAM_CLK between MAC2_CLK and BUS_CLK based on the status of the USB ports.

3 (Val_0x3): In Device mode, selects MAC2_CLK as RAM_CLK. In Host mode, controller switches RAM_CLK between MAC2_CLK and BUS_CLK based on the status of the USB ports.

Reserved.

Core soft reset. Clears the interrupts and all the CSRs except the following registers:

• GCTL
• GUCTL
• GSTS
• GSNPSID
• GUID
• GUSB2PHYCFG0
• DCFG
• DCTL
• DEVTEN
• DSTS Note: This bit is for debug purposes only. Use USBCMD.HCRESET bit in xHCI Mode and the DCTL[SOFTRESET] bit in Device mode for soft reset. Programming this bit field with random data will reset the internal logic of the host controller. Due to this side effect Bit Bash register testing is not recommended.

0 (Val_0x0): No soft reset

1 (Val_0x1): Soft reset to controller

Port capability direction. Note: For static Host-only/Device-only applications, use DRD Host or DRD Device mode. The combination of this bit filed set to 0x3 with SRP and HNP/RSP disabled is not recommended for these applications. The sequence for switching modes in DRD Device mode is as follows:

• For switching from Device to Host:

1. Reset the controller using the CORESOFTRESET bit.
2. Set the PRTCAPDIR bit field to 0x1 (Host mode).
3. Reset the host using USBCMD.HCRESET bit.
4. Follow the steps in Section Initializing Host Registers.

• For switching from Host to Device:

1. Reset the controller using the CORESOFTRESET bit.
2. Set the GCTL[PRTCAPDIR] bit field to 0x2 (Device mode).
3. Reset the device by setting the DCTL[CSFTRST] bit.
4. Follow the steps in Section Initializing Registers. Programming this bit field with random data causes the controller to keep toggling between the Host mode and the Device mode. Bit Bash register testing is not recommended.

1 (Val_0x1): For host configurations

2 (Val_0x2): For device configurations

Frame scales down. This bit field scales down device view of a SOF/USOF/ITP duration. For High Speed (HS) mode:

• Value of 3 implements interval to be 15.625 us
• Value of 2 implements interval to be 31.25 us
• Value of 1 implements interval to be 62.5 us
• Value of 0 implements interval to be 125 us

Bypass set address in Device mode. This bit must be set to 0x0.